Notes on GPU timing, clock synchronisation, embedded systems and AI in production. I'm doing an MSc in Advanced Computing at King's College London, after a year on timing at Intel.
A profiler that patches its own clock reads into the compiled kernel and puts a stated bound on every number. A walk through each diagram: where the timers go, how a single cycle reaches the host clock across eight GPUs, and what happened when I re-timed a published SASS-reordering result.
I work where hardware timing meets software: clock synchronisation, GPU kernels, embedded firmware, and AI systems that run in production.
Before the MSc I spent a year at Intel in the Network & Edge group working on IEEE 1588 PTP, SyncE, NIC drivers and OpenVINO deployments. I graduated from Sussex with a First in Computer Science and AI.
I'm looking for part-time engineering work in London alongside my studies.